Single data item loads and stores:
 VLDR.64            Dd, [Rn{, #<offset>}]   Dd:=[address, size]
 VLDR.64            Dd, [Rn, #-8]!          Rn:=Rn-8; Dd:=[address, size]
 VLDR.64            Dd, [Rn], #8            Dd:=[address, size]; Rn:=Rn+8
 VLDR.64            Dd, label               Dd:=[label, size]
 VLDR.<datatype>    Dd, =constant           Dd:=[label, size]
 VSTR.64            Dd, [Rn{, #<offset>}]   [address, size]:=Dd
 VSTR.64            Dd, label               [label, size]:=Dd
 VSTR.64            Dd, [Rn, #-8]!          Rn:=Rn+8;
                                                    [address, size]:=Dd
 VSTR.64            Dd, [Rn], #8            [address, size]:=Dd;
                                                    Rn:=Rn+8

 <offset>:   Optional multiple of 4 between -1020 and +1020.
             The pre-decrement and post-increment versions are assembled into
              equivalent VLDM or VSTM instructions.
 label:      Word aligned, +/- 1024 bytes from the current instruction.
 <datatype>: <I,U,S><8,16,32,64>, or F32

Other memory operations:
 VLDM{<mode>}   Rn{!}, <registers>
 VPOP                   <registers>             eq. VLDMFD r13!, <registers>
 VPUSH                  <registers>             eq. VSTMFD r13!, <registers>

 <mode>:      IA: increment after (default),
              DB: decrement before,
              EA: empty ascending (DB for loads, IA for stores), or
              FD: full descending (IA for loads, DB for stores)
 <registers>: Can be S, D, or Q registers, but not mixed.
              At most 16 D registers, or 8 Q registers.
              Q registers are translated to their equivalent D registers.

 VLD<n>.<size>      <list1>, [Rn{@<align>}]{!}  D(d+i)[x]:=[address+i*(<size>/8),<size>];
                                                        Rn:=Rn+<n>*(<size>/8)
 VLD<n>.<size>      <list1>, [Rn{@<align>}], Rm D(d+i)[x]:=[address+i*(<size>/8),<size>];
                                                        Rn:=Rn+Rm
 VLD<n>.<size>      <listA>, [Rn{@<align>}]{!}  D(d+i)[x]:=[address+i*(<size>/8),<size>];
                                                        Rn:=Rn+<n>*(<size>/8)
 VLD<n>.<size>      <listA>, [Rn{@<align>}], Rm D(d+i)[x]:=[address+i*(<size>/8),<size>];
                                                        Rn:=Rn+Rm
 VLD<n>.<size>      <list>, [Rn{@<align>}]{!}   D(d+i)[x]:=[address+(x*<n>+i)*(<size>/8),<size>];
                                                        Rn:=Rn+<n>*<size>
 VLD<n>.<size>      <list>, [Rn{@<align>}], Rm  D(d+i)[x]:=[address+(x*<n>+i)*(<size>/8),<size>];
                                                        Rn:=Rn+Rm
 VST<n>.<size>      <list1>, [Rn{@<align>}]{!}  [address+i*(<size>/8),<size>]:=D(d+i)[x]
                                                        Rn:=Rn+<n>*(<size>/8)
 VST<n>.<size>      <list1>, [Rn{@<align>}], Rm [address+i*(<size>/8),<size>]:=D(d+i)[x]
                                                        Rn:=Rn+Rm
 VST<n>.<size>      <list>, [Rn{@<align>}]{!}   [address+(x*<n>+i)*(<size>/8),<size>]:=D(d+i)[x]
                                                        Rn:=Rn+<n>*<size>
 VST<n>.<size>      <list>, [Rn{@<align>}], Rm  [address+(x*<n>+i)*(<size>/8),<size>]:=D(d+i)[x]
                                                        Rn:=Rn+Rm

 Rn:     ARM register other than PC.
 Rm:     ARM register other than r13 or PC.
 <n>:     1, 2, 3, or 4.
 <list1>: {Dd[x],D(d+1)[x],...}, or
          {Dd[x],D(d+2)[x],...}, for <n> > 1, <size> > 8.
 <listA>: {Dd[],D(d+1)[],...}, or {Dd[],D(d+2)[],...} for <n> > 1.
 <list>:  {Dd,D(d+1),...}, or {Dd,D(d+2),...} for <n> > 1.
 <align>: 8, 16, 32, 64, 128, or 256.
 Note: The Dd[] form can fill 1 or 2 registers when <n> == 1 (i.e., D or Q).
       The Dd form can fill 1, 2, 3, or 4 when <n> == 1, and 2 or 4 when
        <n> == 2 (but only 2 when the registers are evenly spaced).
       Otherwise the list must have exactly <n> registers.
 See http://infocenter.arm.com/help/topic/com.arm.doc.dui0489a/CIHEIIGI.html
  for full details.

Move data:
 VMOV               Rd, Sn              Rd:=Sn
 VMOV               Sn, Rd              Sn:=Rd
 VMOV               Dm, Rd, Rn          Dm[63:32]:=Rn; Dm[31:0]:=Rd
 VMOV               Rd, Rn, Dm          Rd:=Dm[31:0]; Rn:=Dm[63:32]
 VMOV               Sm, S(m+1), Rd, Rn  Sm:=Rd; S(m+1):=Rn
 VMOV               Rd, Rn, Sm, S(m+1)  Rd:=Sm; Rn:=S(m+1)
 VMOV{.<size>}      Dn[x], Rd           Dn[(x+1)*size-1:x*size]:=Rd[size-1:0]
 VMOV{.<datatype>}  Rd, Dn[x]           Rd:=Extend(Dn[(x+1)*size-1:x*size]

 Rd, Rn:     ARM registers other than PC.
 <size>:     8, 16, or 32 (default)
 <datatype>: S8, S16, U8, U16, or 32 (default)

 VMOV{.<datatype>}  Qd, Qm              Qd:=Qm
 VMOV{.<datatype>}  Dd, Dm              Dd:=Dm
 VMOV.<datatype>    Qd, #<vimm>         Qd[x]:=#<vimm>
 VMOV.<datatype>    Dd, #<vimm>         Dd[x]:=#<vimm>
 VMVN{.<datatype>}  Qd, Qm              Qd:=~Qm
 VMVN{.<datatype>}  Dd, Dm              Dd:=~Dm
 VMVN.<datatype>    Qd, #<vimm>         Qd[x]:=~#<vimm>
 VMVN.<datatype>    Dd, #<vimm>         Dd[x]:=~#<vimm>
 VSWP{.<datatype>}  Qd, Qm              Swap(Qd,Qm)
 VSWP{.<datatype>}  Dd, Dm              Swap(Dd,Dm)

 <datatype>: Ignored for non-#<vimm> forms.
             I<8,16,32,64> or F32 for VMOV with #<vimm>
             I<16,32> for VMVN with #<vimm>
 <vimm>:     For VMOV form (VMVN requires ~#<vimm> to have one of these forms):
             I8    I16     I32         I64                 F32
             0xXY  0x00XY  0x000000XY  0xGGHHJJKKLLMMNNPP  +/- n*2**-r
                   0xXY00  0x0000XY00   GG...PP must be     16<=n<=31,
                           0x00XY0000   0x00 or 0xFF.       0<=r<=7.
                           0xXY000000

 VMOVL.<datatype>       Qd, Dm          Qd[x]:=Dm[x]
 VMOVN.<datatype>       Dd, Qm          Dd[x]:=(Qm[x])
 V{Q}MOVN.<datatype>    Dd, Qm          Dd[x]:=Saturate(Qm[x])
 VQMOVUN.<datatype>     Dd, Qm          Dd[x]:=UnsignedSat(Qm[x])

 <datatype>: S<8,16,32> or U<8,16,32> for VMOVL
             I<16,32,64> for VMOVN
             S<16,32,64> or U<16,32,64> for VQMOVN
             S<16,32,64> for VQMOVUN

 VDUP.<size>        Qd, Dm[x]           Qd[y]:=Dm[x]
 VDUP.<size>        Dd, Dm[x]           Dd[y]:=Dm[x]
 VDUP.<size>        Qd, Rm              Qd[y]:=Rm
 VDUP.<size>        Dd, Rm              Dd[y]:=Rm

 <size>: 8, 16, or 32
 Rm:     ARM register other than PC.

 VEXT.<size>        {Qd,} Qn, Qm, #immX Qd[x]:=(Qm:Qn)[x+#immX]
 VEXT.<size>        {Dd,} Dn, Dm, #immX Dd[x]:=(Dm:Dn)[x+#immX]

 <size>: 8, 16, 32, or 64.
         Assembled to the equivalent .8 form.
 <immX>: 0 to 64/<size>-1 for doublewords, 128/<size>-1 for quadwords.

 VREV<n>.<size>     Qd, Qm              Qd[x*(<n>/<size>)+y]:=Qm[(x+1)*(<n>/<size>)-y-1]
 VREV<n>.<size>     Dd, Dm              Dd[x*(<n>/<size>)+y]:=Dm[(x+1)*(<n>/<size>)-y-1]

 <n>:    16, 32, or 64.
 <size>: 8, 16, or 32, with <size> < <n>.

 VTBL.8             Dd, <list>, Dm      Dd[x]:=<list>[Dm[x]]
 VTBX.8             Dd, <list>, Dm      Dd[x]:=Dm[x] < size(<list>)?<list>[Dm[x]]:Dd[x]

 <list>: {Dn}, {Dn,D(n+1)}, {Dn,D(n+1),D(n+2)}, {Dn,D(n+1),D(n+2),D(n+3)}, or
          {Qn,Q(n+1)}.
         May not wrap around the reigster bank.
         Q registers are assembled to their equivalent D registers.

 VTRN.<size>        Qd, Qm              Swap(Qd[2*x+1],Qm[2*x])
 VTRN.<size>        Dd, Dm              Swap(Qd[2*x+1],Qm[2*x])

 <size>: 8, 16, or 32.

 VZIP.<size>        Qd, Qm              (Qm:Qd)[2*x]:=Qd[x]; (Qm:Qd)[2*x+1]:=Qm[x]
 VZIP.<size>        Dd, Dm              (Dm:Dd)[2*x]:=Dd[x]; (Dm:Dd)[2*x+1]:=Dm[x]
 Qd.32 =  D C B A  =>  F B E A
 Qm.32 =  H G F E  =>  H D G C
           or
 Qd.32 =  G E C A  =>  D C B A
 Qm.32 =  H F D B  = > H G F E

 VUZP.<size>        Qd, Qm              Qd[x]:=(Qm:Qd)[2*x]; Qm[x]:=(Qm:Qd)[2*x+1]
 VUZP.<size>        Dd, Dm              Dd[x]:=(Dm:Dd)[2*x]; Dm[x]:=(Dm:Dd)[2*x+1]
 Qd.32 =  D C B A  =>  G E C A
 Qm.32 =  H G F E  =>  H F D B
           or
 Qd.32 =  F B E A  =>  D C B A
 Qm.32 =  H D G C  =>  H G F E

Shift:
 VSHL.<datatype>        {Qd,} Qm, #<immD>   Qd[x]:=Qm[x]<<#<immD>
 VSHL.<datatype>        {Dd,} Dm, #<immD>   Dd[x]:=Dm[x]<<#<immD>
 VQSHL.<datatype>       {Qd,} Qm, #<immD>   Qd[x]:=Saturate(Qm[x]<<#<immD>)
 VQSHL.<datatype>       {Dd,} Dm, #<immD>   Dd[x]:=Saturate(Dm[x]<<#<immD>)
 VQSHLU.<datatype>      {Qd,} Qm, #<immD>   Qd[x]:=UnsignedSat(Qm[x]<<#<immD>)
 VQSHLU.<datatype>      {Dd,} Dm, #<immD>   Dd[x]:=UnsignedSat(Dm[x]<<#<immD>)
 VSHLL.<datatype>       Qd, Dm, #<immE>     Qd[x]:=Extend(Dm[x])<<#<immD>
 V{R}SHL.<datatype>     {Qd,} Qm, Qn        Qd[x]:=s<0?Qm[x]+({R}?1<<-s>>1:0)>>-s:Qm[x]<<s, s=Qn[x][7:0]
 VQ{R}SHL.<datatype>    {Qd,} Qm, Qn        Qd[x]:=s<0?Qm[x]+({R}?1<<-s>>1:0)>>-s:Saturate(Qm[x]<<s), s=Qn[x][7:0]
 V{R}SHR.<datatype>     {Qd,} Qm, #<immD>   Qd[x]:=Qm[x]+({R}?1<<#<immD>>>1:0)>>#<immD>
 V{R}SHR.<datatype>     {Dd,} Dm, #<immD>   Dd[x]:=Dm[x]+({R}?1<<#<immD>>>1:0)>>#<immD>
 V{R}SRA.<datatype>     {Qd,} Qm, #<immD>   Qd[x]:=Qd[x]+(Qm[x]+({R}?1<<#<immD>>>1:0)>>#<immD>)
 V{R}SRA.<datatype>     {Dd,} Dm, #<immD>   Dd[x]:=Dd[x]+(Dm[x]+({R}?1<<#<immD>>>1:0)>>#<immD>)
 V{R}SHRN.<datatype>    Dd, Qm, #<immD>     Dd[x]:=Qm[x]+({R}?1<<#<immD>>>1:0)>>#<immD>
 VQ{R}SHRN.<datatype>   Dd, Qm, #<immD>     Dd[x]:=Saturate(Qm[x]+({R}?1<<#<immD>>>1:0)>>#<immD>)
 VQ{R}SHRUN.<datatype>  Dd, Qm, #<immD>     Dd[x]:=UnsignedSat(Qm[x]+({R}?1<<#<immD>>>1:0)>>#<immD>)
 VSLI.<size>            {Qd,} Qm, #<immD>   Qd[x][<size>-1:#<immD>]:=Qm[x][<size>-#<immD>-1:0]
 VSLI.<size>            {Dd,} Dm, #<immD>   Dd[x][<size>-1:#<immD>]:=Dm[x][<size>-#<immD>-1:0]
 VSRI.<size>            {Qd,} Qm, #<immD>   Qd[x][<size>-#<immD>-1:0]:=Qm[x][<size>-1:#<immD>]
 VSRI.<size>            {Dd,} Dm, #<immD>   Dd[x][<size>-#<immD>-1:0]:=Dm[x][<size>-1:#<immD>]

 <datatype>: I<8,16,32,64> for VSHL,
             S<8,16,32,64> or U<8,16,32,64> for VQSHL, V{Q}RSHL, V{R}SHR,
              or V{R}SRA,
             S<8,16,32,64> for VQSHLU,
             S<8,16,32> or U<8,16,32> for VSHLL,
             I<16,32,64> for V{R}SHRN,
             S<16,32,64> or U<16,32,64> for VQ{R}SHRN,
             S<16,32,64> for VQSHRNU.
 <size>:     8, 16, 32, or 64.
 <immD>:     1 to size(<datatype>)-1.
             0 is permitted but is assembled to VMOV for V{Q}{R}SHL.
 <immE>:     1 to size(<datatype>).
             0 is permitted but is assembled to VMOVL.

Logical:
 V<op>{.<datatype>} {Qd,} Qn, Qm
 V<op>{.<datatype>} {Dd,} Dn, Dm

 <op>:       AND, EOR, ORR, ORN, or BIC.
 <datatype>: Ignored.
 VORR with {Q,D}n == {Q,D}m is assembled as VMOV.

 V<op>{.<datatype>} Qd, #<vimm>
 V<op>{.<datatype>} Dd, #<vimm>

 <op>:       ORR or BIC, or AND or ORN if they can be converted to an
              equivalent BIC or ORR.
 <datatype>: I{8,16,32,64}.
 <vimm>:     I16     I32
             0x00XY  0x000000XY
             0xXY00  0x0000XY00
                     0x00XY0000
                     0xXY000000
 I8 or I64 get converted to I16 or I32 equivalents, or generate an error.

Bitwise Select:
 VBIT{.<datatype>} {Qd,} Qn, Qm         Qd[i]:=Qm[i]?Qn[i]:Qd[i]
 VBIT{.<datatype>} {Dd,} Dn, Dm         Dd[i]:=Dm[i]?Dn[i]:Dd[i]
 VBIF{.<datatype>} {Qd,} Qn, Qm         Qd[i]:=Qm[i]?Qd[i]:Qn[i]
 VBIF{.<datatype>} {Dd,} Dn, Dm         Dd[i]:=Dm[i]?Dd[i]:Dn[i]
 VBSL{.<datatype>} {Qd,} Qn, Qm         Qd[i]:=Qd[i]?Qn[i]:Qm[i]
 VBSL{.<datatype>} {Dd,} Dn, Dm         Dd[i]:=Dd[i]?Qn[i]:Qm[i]

 <datatype>: Ignored.

Compare:
 VC<op>.<datatype>       {Qd,} Qn, Qm   Qd[x]:=-(Qn[x]<op>Qm[x])
 VC<op>.<datatype>       {Dd,} Dn, Dm   Dd[x]:=-(Dn[x]<op>Dm[x])
 VC<op>.<datatype>       {Qd,} Qn, #0   Qd[x]:=-(Qn[x]<op>#0)
 VC<op>.<datatype>       {Dd,} Dn, #0   Dd[x]:=-(Dn[x]<op>#0)

 <op>:       EQ, GE, GT, LE, or LT.
             VCLE and VCLT with vector operands are assembled into VCGT and
              VCGE with the operands reversed.
 <datatype>: I<8,16,32> or F32 for EQ,
             S<8,16,32>, U<8,16,32>, or F32 for GE, GT, LE, or LT,
             S<8,16,32> or F32 for GE, GT, LE, LT (#0 form).

 VTST.<size>        {Qd,} Qn, Qm        Qd[x]:=-((Qn[x]&Qm[x])!=0)
 VTST.<size>        {Dd,} Dn, Dm        Dd[x]:=-((Dn[x]&Dm[x])!=0)

 <size>: 8, 16, or 32

Arithmetic:
 VABD.<datatype>    {Qd,} Qn, Qm        Qd[x]:=Abs(Qn[x]-Qm[x])
 VABD.<datatype>    {Dd,} Dn, Dm        Dd[x]:=Abs(Dn[x]-Dm[x])
 VABDL.<datatype>   Qd, Dn, Dm          Qd[x]:=Abs(Dn[x]-Dm[x])
 VABA.<datatype>    {Qd,} Qn, Qm        Qd[x]:=Qd[x]+Abs(Qn[x]-Qm[x])
 VABA.<datatype>    {Dd,} Dn, Dm        Dd[x]:=Dd[x]+Abs(Dn[x]-Dm[x])
 VABAL.<datatype>   Qd, Dn, Dm          Qd[x]:=Qd[x]+Abs(Dn[x]-Dm[x])

 <datatype>: <S,U><8,16,32> for VABA{L} or VABDL,
             <S,U><8,16,32> or F32 for VABD.

 VABS.<datatype>    Qd, Qm              Qd[x]:=Abs(Qn[x])
 VABS.<datatype>    Dd, Dm              Dd[x]:=Abs(Dn[x])
 VQABS.<datatype>   Qd, Qm              Qd[x]:=UnsignedSat(Abs(Qn[x]))
 VQABS.<datatype>   Dd, Dm              Dd[x]:=UnsignedSat(Abs(Dn[x]))
 VNEG.<datatype>    Qd, Qm              Qd[x]:=-Qn[x]
 VNEG.<datatype>    Dd, Dm              Dd[x]:=-Dn[x]
 VQNEG.<datatype>   Qd, Qm              Qd[x]:=SignedSat(-Qn[x])
 VQNEG.<datatype>   Dd, Dm              Dd[x]:=SignedSat(-Dn[x])

 <datatype>: S<8,16,32> for VQABS or VQNEG,
             S<8,16,32> or F32 for VABS or VNEG.

 VADD.<datatype>    {Qd,} Qn, Qm        Qd[x]:=Qn[x]+Qm[x]
 VADD.<datatype>    {Dd,} Dn, Dm        Dd[x]:=Dn[x]+Dm[x]
 VSUB.<datatype>    {Qd,} Qn, Qm        Qd[x]:=Qn[x]-Qm[x]
 VSUB.<datatype>    {Dd,} Dn, Dm        Dd[x]:=Dn[x]-Dm[x]
 VQADD.<datatype>   {Qd,} Qn, Qm        Qd[x]:=Saturate(Qn[x]+Qm[x])
 VQADD.<datatype>   {Dd,} Dn, Dm        Dd[x]:=Saturate(Dn[x]+Dm[x])
 VQSUB.<datatype>   {Qd,} Qn, Qm        Qd[x]:=Saturate(Qn[x]-Qm[x])
 VQSUB.<datatype>   {Dd,} Dn, Dm        Dd[x]:=Saturate(Dn[x]-Dm[x])
 VADDL.<datatype>   Qd, Dn, Dm          Qd[x]:=Dn[x]+Dm[x]
 VSUBL.<datatype>   Qd, Dn, Dm          Qd[x]:=Dn[x]-Dm[x]
 VADDW.<datatype>   {Qd,} Qn, Dm        Qd[x]:=Qn[x]+Dm[x]
 VSUBW.<datatype>   {Qd,} Qn, Dm        Qd[x]:=Qn[x]-Dm[x]

 <datatype>: I<8,16,32,64> or F32 for VADD or VSUB,
             <S,U><8,16,32,64> for VQADD or VQSUB,
             <S,U><8,16,32> for VADD<L,W> or VSUB<L,W>.

 V{R}ADDHN.<datatype>   Dd, Qn, Qm      Dd[x]:=(Qn[x]+Qm[x]+({R}?1<<s/2-1:0))[s-1:s/2], s=size(<datatype>)
 V{R}SUBHN.<datatype>   Dd, Qn, Qm      Dd[x]:=(Qn[x]-Qm[x]+({R}?1<<s/2-1:0))[s-1:s/2], s=size(<datatype>)

 <datatype>: I<16,32,64>

 V{R}HADD.<datatype>    Dd, Qn, Qm      Dd[x]:=Qn[x]+Qm[x]+({R}?1:0)>>1
 V{R}HSUB.<datatype>    Dd, Qn, Qm      Dd[x]:=Qn[x]+Qm[x]+({R}?1:0)>>1

 <datatype>: <S,U><8,16,32>

 VPADD.<dataype>    {Dd,} Dn, Dm        Dd[x]:=(Dm:Dn)[2*x]+(Dm:Dn)[2*x+1]
 VPADDL.<datatype>  Qd, Qm              Qd[x]:=Qm[2*x]+Qm[2*x+1]
 VPADDL.<datatype>  Dd, Dm              Dd[x]:=Dm[2*x]+Dm[2*x+1]
 VPADAL.<datatype>  Qd, Qm              Qd[x]:=Qd[x]+Qm[2*x]+Qm[2*x+1]
 VPADAL.<datatype>  Dd, Dm              Dd[x]:=Dd[x]+Dm[2*x]+Dm[2*x+1]

 <datatype>: I<8,16,32> or F32 for VPADD,
             <S,U><8,16,32> for VPADDL or VPADAL.

 VMAX.<datatype>    Qd, Qn, Qm          Qd[x]:=Max(Qn[x],Qm[x])
 VMAX.<datatype>    Dd, Dn, Dm          Dd[x]:=Max(Dn[x],Dm[x])
 VMIN.<datatype>    Qd, Qn, Qm          Qd[x]:=Min(Qn[x],Qm[x])
 VMIN.<datatype>    Dd, Dn, Dm          Dd[x]:=Min(Dn[x],Dm[x])
 VPMAX.<datatype>   Dd, Dn, Dm          Dd[x]:=Max((Dm:Dn)[2*x],(Dm:Dn)[2*x+1])
 VPMIN.<datatype>   Dd, Dn, Dm          Dd[x]:=Min((Dm:Dn)[2*x],(Dm:Dn)[2*x+1])

 <datatype>: <S,U><8,16,32> or F32.

 VCLS.<datatype>    Qd, Qm              Qd[x]:=Clz(Qm[x]^-Qm[x][size(<datatype>)-1])
 VCLZ.<datatype>    Qd, Qm              Qd[x]:=Clz(Qm[x])
 VCNT.<datatype>    Qd, Qm              Qd[x]:=PopCount(Qm[x])

 <datatype>: S<8,16,32> for VCLS,
             I<8,16,32> for VCLZ,
             I8 for VCNT.

 VMUL.<datatype>        {Qd,} Qn, Qm    Qd[x]:=Qn[x]*Qm[x]
 VMUL.<datatype>        {Dd,} Dn, Dm    Dd[x]:=Dn[x]*Dm[x]
 VMUL.<datatype>        {Qd,} Qn, Dm[x] Qd[y]:=Qn[y]*Dm[x]
 VMUL.<datatype>        {Dd,} Dn, Dm[x] Dd[y]:=Dn[y]*Dm[x]
 VMLA.<datatype>        {Qd,} Qn, Qm    Qd[x]:=Qd[x]+Qn[x]*Qm[x]
 VMLA.<datatype>        {Dd,} Dn, Dm    Dd[x]:=Dd[x]+Dn[x]*Dm[x]
 VMLA.<datatype>        {Qd,} Qn, Dm[x] Qd[y]:=Qd[y]+Qn[y]*Dm[x]
 VMLA.<datatype>        {Dd,} Dn, Dm[x] Dd[y]:=Dd[y]+Dn[y]*Dm[x]
 VMLS.<datatype>        {Qd,} Qn, Qm    Qd[x]:=Qd[x]-Qn[x]*Qm[x]
 VMLS.<datatype>        {Dd,} Dn, Dm    Dd[x]:=Dd[x]-Dn[x]*Dm[x]
 VMLS.<datatype>        {Qd,} Qn, Qm[x] Qd[y]:=Qd[y]-Qn[y]*Dm[x]
 VMLS.<datatype>        {Dd,} Dn, Dm[x] Dd[y]:=Dd[y]-Dn[y]*Dm[x]
 VMULL.<datatype>       Qd, Dn, Dm      Qd[x]:=Dn[x]*Dm[x]
 VMULL.<datatype>       Qd, Dn, Dm[x]   Qd[y]:=Dn[y]*Dm[x]
 VMLAL.<datatype>       Qd, Dn, Dm      Qd[x]:=Qd[x]+Dn[x]*Dm[x]
 VMLAL.<datatype>       Qd, Dn, Dm[x]   Qd[y]:=Qd[y]+Dn[y]*Dm[x]
 VMLSL.<datatype>       Qd, Dn, Dm      Qd[x]:=Qd[x]-Dn[x]*Dm[x]
 VMLSL.<datatype>       Qd, Dn, Dm[x]   Qd[y]:=Qd[y]-Dn[y]*Dm[x]
 VQDMULL.<datatype>     Qd, Dn, Dm      Qd[x]:=Saturate(2*Dn[x]*Dm[x])
 VQDMULL.<datatype>     Qd, Dn, Dm[x]   Qd[y]:=Saturate(2*Dn[y]*Dm[x])
 VQDMLAL.<datatype>     Qd, Dn, Dm      Qd[x]:=Saturate(Qd[x]+2*Dn[x]*Dm[x])
 VQDMLAL.<datatype>     Qd, Dn, Dm[x]   Qd[y]:=Saturate(Qd[y]+2*Dn[y]*Dm[x])
 VQDMLSL.<datatype>     Qd, Dn, Dm      Qd[x]:=Saturate(Qd[x]-2*Dn[x]*Dm[x])
 VQDMLSL.<datatype>     Qd, Dn, Dm[x]   Qd[y]:=Saturate(Qd[y]-2*Dn[y]*Dm[x])
 VQ{R}DMULH.<datatype>  {Qd,} Qn, Qm    Qd[x]:=Saturate(2*Qn[x]*Qm[x]+({R}?1<<s-1:0))[2*s-1:s], s=size(<datatype>)
 VQ{R}DMULH.<datatype>  {Dd,} Dn, Dm    Dd[x]:=Saturate(2*Dn[x]*Dm[x]+({R}?1<<s-1:0))[2*s-1:s], s=size(<datatype>)
 VQ{R}DMULH.<datatype>  {Qd,} Qn, Qm[x] Qd[y]:=Saturate(2*Qn[y]*Qm[x]+({R}?1<<s-1:0))[2*s-1:s], s=size(<datatype>)
 VQ{R}DMULH.<datatype>  {Dd,} Dn, Dm[x] Dd[y]:=Saturate(2*Dn[y]*Dm[x]+({R}?1<<s-1:0))[2*s-1:s], s=size(<datatype>)

 <datatype>: I<8,16,32>, F32, or P8 for VMUL, VMLA, or VMLS,
             <S,U><8,16,32> or P8 for VMULL,
             <S,U><8,16,32> for VMULL, VMLAL, or VMLSL,
             S<16,32> for VQ{R}DMUL<L,H>, VQ{R}DMLA<L,H>, or VQ{R}DMLS<L,H>.
             8-bit datatypes are not available for scalar versions.
             The doubled multiplies do not support 8-bit datatypes nor unsigned
              datatypes.

Move to or from PSR:
 VMRS               Rd, <extsysreg>     Rd:=<extsysreg>
 VMSR               <extsysreg>, Rd     <extsysreg>:=Rd

 <extsysreg>: Usually FPSCR, FPSID, or FPEXC.
 Rd:          ARM register other than PC, or APSR_nzcv if <extsysreg> is FPSCR.

Floating-point only:
 VAC<op>.F32       {Qd,} Qn, Qm         Qd[x]:=-(fabs(Qn[x])<op>fabs(Qm[x]))
 VAC<op>.F32       {Dd,} Dn, Dm         Dd[x]:=-(fabs(Dn[x])<op>fabs(Dm[x]))

 <op>: GE, GT, LE, or LT.
       VACLE and VACLT are assembled into VACGT and VACGE with the operands
        reversed.

PMOVMSKB:
; 8-bit
VNEG.S8 D0, D0
VMOV    r0, r1, D0
ORR     r0, r0, r1, LSL #4
ORR     r0, r0, r0, LSR #7
ORR     r0, r0, r0, LSR #14
UXTB    r0, r0

; 16-bit
VNEG.S8 Q0, Q0
VZIP.8  D0, D1
VSLI.8  D0, D1, #4
VMOV    r0, r1, D0
ORR     r0, r0, r1, LSL #2
ORR     r0, r0, r0, LSR #15
UXTH    r0, r0

Legacy opcode names:
VFMX      -> VPMAX
VFMN      -> VPMIN
VQ{R}DMLH -> VQ{R}DMULH
VCAGE     -> VACGE
VCAGT     -> VACGT
VSUM[L]   -> VPADD[L]
V{R}ADH   -> V{R}ADDHN
V{R}SBH   -> V{R}SUBHN
VQ{R}DMLH -> VQ{R}DMULH
VMVHW     -> VSHLL
VSMAL     -> VPADAL

gcc register names:
r10 -> sl
r11 -> fp
r12 -> ip
r13 -> sp
r14 -> lr
r15 -> pc